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» A routing algorithm for flip-chip design
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ISPD
2004
ACM
92views Hardware» more  ISPD 2004»
14 years 2 months ago
A predictive distributed congestion metric and its application to technology mapping
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for...
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant S...
DAC
2008
ACM
14 years 10 months ago
Concurrent topology and routing optimization in automotive network integration
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
Bardo Lang, Christian Haubelt, Jürgen Teich, ...
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 9 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
14 years 1 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
ANCS
2006
ACM
14 years 2 months ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu