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DATE
2003
IEEE
145views Hardware» more  DATE 2003»
14 years 21 hour ago
Automated Bus Generation for Multiprocessor SoC Design
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
Kyeong Keol Ryu, Vincent John Mooney
ISQED
2006
IEEE
116views Hardware» more  ISQED 2006»
14 years 22 days ago
Probabilistic Delay Budgeting for Soft Realtime Applications
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
Soheil Ghiasi, Po-Kuan Huang
EH
2000
IEEE
183views Hardware» more  EH 2000»
13 years 11 months ago
A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
Ricardo Salem Zebulum, Cristina Costa Santini, Hel...
SIGPRO
2011
275views Hardware» more  SIGPRO 2011»
12 years 9 months ago
Synthesis of multivariate stationary series with prescribed marginal distributions and covariance using circulant matrix embeddi
The problem of synthesizing multivariate stationary series Y [n] = (Y1[n], . . . , YP [n])T , n ∈ Z, with prescribed non-Gaussian marginal distributions, and a targeted covarian...
Hannes Helgason, Vladas Pipiras, Patrice Abry
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
13 years 10 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...