Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
The recent emergence of multi-core processors enables a new trend in the usage of computers. Computer vision applications, which require heavy computation and lots of bandwidth, u...
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
Brian F. Veale, John K. Antonio, Monte P. Tull, S....
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
Power consumption has become a major constraint in the design of processors today. To optimize a processor for energyefficiency requires an examination of energy-performance trade...
Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay...