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ASPLOS
1996
ACM
14 years 1 months ago
A Quantitative Analysis of Loop Nest Locality
This paper analyzes and quantifies the locality characteristics of numerical loop nests in order to suggest future directions for architecture and software cache optimizations. Si...
Kathryn S. McKinley, Olivier Temam
CODES
2004
IEEE
14 years 22 days ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
CODES
2004
IEEE
14 years 22 days ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
BMCBI
2007
159views more  BMCBI 2007»
13 years 9 months ago
sIR: siRNA Information Resource, a web-based tool for siRNA sequence design and analysis and an open access siRNA database
Background: RNA interference has revolutionized our ability to study the effects of altering the expression of single genes in mammalian (and other) cells through targeted knockdo...
Jyoti K. Shah, Harold R. Garner, Michael A. White,...
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
14 years 3 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...