214 search results - page 13 / 43 » A system level design methodology for the optimization of he... |
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
CODES
2003
IEEE
14 years 28 days ago
2003
IEEE
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—In embedded computing we face a continuously growing algorithm complexity combined with a constantly rising number of applications running on a single system. Multi-core systems...
ISSS
1999
IEEE
13 years 12 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...