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    » A technique for minimizing power during FPGA placement
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    ERSA
    2009
    147views Hardware» more  ERSA 2009»
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    13 years 6 months ago
    Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
    Download  eecs.wsu.edu
    Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
    Kylan Robinson, José G. Delgado-Frias
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    DAC
    2005
    ACM
    184views Computer Architecture» more  DAC 2005»
    An effective power mode transition technique in MTCMOS circuits
    14 years 9 months ago
    An effective power mode transition technique in MTCMOS circuits
    Download  atrak.usc.edu
    - The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in ...
    Afshin Abdollahi, Farzan Fallah, Massoud Pedram
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    MICRO
    2005
    IEEE
    113views Hardware» more  MICRO 2005»
    Thermal Management of On-Chip Caches Through Power Density Minimization
    14 years 2 months ago
    Thermal Management of On-Chip Caches Through Power Density Minimization
    Download  cucis.ece.northwestern.edu
    Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
    Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
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    ISLPED
    2005
    ACM
    111views Hardware» more  ISLPED 2005»
    Peak temperature control and leakage reduction during binding in high level synthesis
    14 years 2 months ago
    Peak temperature control and leakage reduction during binding in high level synthesis
    Download  www.eecs.northwestern.edu
    Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
    Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
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    DAC
    2011
    ACM
    250views Computer Architecture» more  DAC 2011»
    Thermal-aware cell and through-silicon-via co-placement for 3D ICs
    12 years 8 months ago
    Thermal-aware cell and through-silicon-via co-placement for 3D ICs
    Download  cadlab.cs.ucla.edu
    Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
    Jason Cong, Guojie Luo, Yiyu Shi
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