118 search results - page 6 / 24 » A technique for minimizing power during FPGA placement |
ICCAD
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
JCP
2008
13 years 7 months ago
2008
Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
VTS
2008
IEEE
14 years 1 months ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...