118 search results - page 9 / 24 » A technique for minimizing power during FPGA placement |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
This paper examines various activity estimation techniques in order to determine which are most appropriate for use in the context of field-programmable gate arrays (FPGAs). Speci...
DATE
2010
IEEE
14 years 14 days ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
The main goal of this paper is to develop deeper insights into viable placement-level optimization of routing. Two primary contributions are made. First, an experimental framework...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...