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TVLSI
2010
13 years 2 months ago
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...
Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang
DAC
2004
ACM
14 years 8 months ago
Quantum logic synthesis by symbolic reachability analysis
Reversible quantum logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability anal...
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Y...
TCAD
1998
82views more  TCAD 1998»
13 years 7 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
CONPAR
1992
13 years 11 months ago
Analysis of an Efficient Distributed Algorithm for Mutual Exclusion (Average-Case Analysis of Path Reversal)
The algorithm designed in [12, 15] was the very first distributed algorithm to solve the mutual exclusion problem in complete networks by using a dynamic logical tree structure as...
Christian Lavault
CDES
2008
87views Hardware» more  CDES 2008»
13 years 9 months ago
Finding Minimal ESCT Expressions for Boolean Functions with Weight of up to 7
In this paper an algorithm is proposed for the synthesis and exact minimization of ESCT (Exclusive or Sum of Complex Terms) expressions for Boolean functions of up to seven comple...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...