Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
Andrew Carlson, Zheng Guo, Sriram Balasubramanian,...
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia...
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility ...
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...