48 search results - page 6 / 10 » AHIR: A Hardware Intermediate Representation for Hardware Ge... |
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
ECBS
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
CVPR
2011
IEEE
13 years 2 months ago
2011
IEEE
We propose a new method to quickly and accurately predict 3D positions of body joints from a single depth image, using no temporal information. We take an object recognition appro...
FPL
2001
Springer
13 years 11 months ago
2001
Springer
Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image pr...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...