47 search results - page 7 / 10 » Accelerated costas array enumeration using FPGAs |
IPPS
1999
IEEE
14 years 5 days ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
CASES
2008
ACM
13 years 10 months ago
2008
ACM
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
TVLSI
2008
13 years 7 months ago
2008
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
BMCBI
2008
13 years 8 months ago
2008
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...