14 search results - page 3 / 3 » Accelerating HMMer on FPGAs using systolic array based archi... |
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
CF
2009
ACM
14 years 1 months ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
DAC
2004
ACM
14 years 26 days ago
2004
ACM
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...