229 search results - page 6 / 46 » Accelerating SIFT on parallel architectures |
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
MVA
2011
13 years 2 months ago
2011
Abstract This paper describes novel implementations of the KLT feature tracking and SIFT feature extraction algorithms that run on the graphics processing unit (GPU) and is suitabl...
FPL
1998
Springer
13 years 11 months ago
1998
Springer
This paper discusses the memory interface of custom computing machines. We present a high speed parallel memory for the MoM-PDA machine, which is based on the Xputer paradigm. The ...
CODES
2005
IEEE
14 years 29 days ago
2005
IEEE
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...