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ICES
2001
Springer
91views Hardware» more  ICES 2001»
13 years 11 months ago
Untidy Evolution: Evolving Messy Gates for Fault Tolerance
Abstract. The exploitation of the physical characteristics has already been demonstrated in the intrinsic evolution of electronic circuits. This paper is an initial attempt at crea...
Julian F. Miller, Morten Hartmann
IPPS
2003
IEEE
14 years 17 days ago
Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMar...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
13 years 10 months ago
On the Risk of Fault Coupling over the Chip Substrate
—Duplication and comparison has proven to be an efficient method for error detection. Based on this generic principle dual core processor architectures with output comparison ar...
Peter Tummeltshammer, Andreas Steininger
JSS
2000
97views more  JSS 2000»
13 years 7 months ago
Exploring the relationships between design measures and software quality in object-oriented systems
The first goal of this paper is to empirically explore the relationships between existing object-oriented coupling, cohesion, and inheritance measures and the probability of fault...
Lionel C. Briand, Jürgen Wüst, John W. D...
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
14 years 1 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...