81 search results - page 9 / 17 » Accurate microarchitecture-level fault modeling for studying... |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
Abstract— In this paper we study the testability of circuits derived from Binary Decision Diagrams (BDDs) under the bridging fault model. It is shown that testability can be form...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Designing cost-sensitive real-time control systems for safetycritical applications requires a careful analysis of the cost/coverage trade-offs of fault-tolerant solutions. This fu...
ICES
2003
Springer
14 years 15 days ago
2003
Springer
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Abstract—The slack time in real-time systems can be used by recovery schemes to increase system reliability as well as by frequency and voltage scaling techniques to save energy....
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...