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» Achievable Performance of Digital Watermarking Systems
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CODES
2011
IEEE
12 years 7 months ago
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are ...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
MST
2006
136views more  MST 2006»
13 years 7 months ago
Simple Efficient Load-Balancing Algorithms for Peer-to-Peer Systems
Load balancing is a critical issue for the efficient operation of peerto-peer networks. We give two new load-balancing protocols whose provable performance guarantees are within a...
David R. Karger, Matthias Ruhl
VRST
2004
ACM
14 years 29 days ago
A CAVE system for interactive modeling of global illumination in car interior
Global illumination dramatically improves realistic appearance of rendered scenes, but usually it is neglected in VR systems due to its high costs. In this work we present an effi...
Kirill Dmitriev, Thomas Annen, Grzegorz Krawczyk, ...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 23 days ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
DATE
2008
IEEE
171views Hardware» more  DATE 2008»
14 years 2 months ago
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...