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DAC
2010
ACM
13 years 9 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
CGO
2007
IEEE
14 years 3 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
SIGMETRICS
2008
ACM
13 years 8 months ago
Scheduling despite inexact job-size information
Motivated by the optimality of Shortest Remaining Processing Time (SRPT) for mean response time, in recent years many computer systems have used the heuristic of "favoring sm...
Adam Wierman, Misja Nuyens
DAC
2002
ACM
14 years 9 months ago
A flexible accelerator for layer 7 networking applications
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
Gokhan Memik, William H. Mangione-Smith
ISCAS
2006
IEEE
154views Hardware» more  ISCAS 2006»
14 years 2 months ago
A novel Fisher discriminant for biometrics recognition: 2DPCA plus 2DFLD
— this paper presents a novel image feature extraction and recognition method two dimensional linear discriminant analysis (2DLDA) in a much smaller subspace. Image representatio...
R. M. Mutelo, Li Chin Khor, Wai Lok Woo, Satnam Si...