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» Activity Estimation for Field-Programmable Gate Arrays
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IJCAT
2010
273views more  IJCAT 2010»
13 years 6 months ago
FPGA implementation of log-polar mapping
Log-polar or spatially-variant image representation is an important component of active vision system in tracking process for many robotic applications due to its data compression ...
Wai Kit Wong, Chee Wee Choo, Chu Kiong Loo, Joo Pe...
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 4 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
14 years 1 months ago
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...
Jawad Khan, Ranga Vemuri
DAC
2003
ACM
14 years 8 months ago
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
Byoungro So, Pedro C. Diniz, Mary W. Hall