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» Activity-driven clock design for low power circuits
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HPCC
2007
Springer
16 years 3 days ago
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to ef...
Yong Li, Zhiying Wang, Jian Ruan, Kui Dai
SENSYS
2009
ACM
15 years 10 months ago
A tale of two synchronizing clocks
A specific application for wastewater monitoring and actuation, called CSOnet, deployed city-wide in a mid-sized US city, South Bend, Indiana, posed some challenges to a time syn...
Jinkyu Koo, Rajesh Krishna Panta, Saurabh Bagchi, ...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
16 years 5 hour ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
15 years 11 months ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
DAC
1998
ACM
15 years 10 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha