140 search results - page 6 / 28 » Activity-sensitive architectural power analysis for the cont... |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
TIM
2010
13 years 2 months ago
2010
In this paper, the authors propose and analyze a network-based control architecture for power-electronicsbuilding-block-based converters. The objective of the proposed approach is ...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
CGO
2004
IEEE
13 years 11 months ago
2004
IEEE
Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method fo...
TWC
2008
13 years 7 months ago
2008
In this paper the performance of the reverse link of a multicell DS-CDMA system with coexisting open-loop and closed-loop power controlled users transmitting heterogeneous traffic ...