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» Adapting an SoC to ATE Concurrent Test Capabilities
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ITC
2002
IEEE
102views Hardware» more  ITC 2002»
14 years 3 months ago
Adapting an SoC to ATE Concurrent Test Capabilities
Rainer Dorsch, Ramón Huerta Rivera, Hans-Jo...
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 5 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
DATE
2007
IEEE
143views Hardware» more  DATE 2007»
14 years 5 months ago
Portable multimedia SoC design: a global challenge
- The intrinsic capability brought by each new technology node opens the way to a broad range of system integration options and continuously enables new applications to be integrat...
Maurizio Paganini, Georg Kimmich, Stephane Ducrey,...
TVLSI
2008
105views more  TVLSI 2008»
13 years 10 months ago
Robust Concurrent Online Testing of Network-on-Chip-Based SoCs
Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in reliability motivate the development of solutions to ensure reliable operation. A precurso...
Praveen Bhojwani, Rabi N. Mahapatra
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
14 years 2 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...