3 search results - page 1 / 1 » Additive Approximation for Layer Minimization of Manhattan S... |
ENDM
2010
13 years 5 months ago
2010
ISPD
2009
ACM
14 years 5 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ICCAD
2008
IEEE
14 years 7 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...