25 search results - page 4 / 5 » Address Bus Encoding Techniques for System-Level Power Optim... |
DATE
2005
IEEE
14 years 18 days ago
2005
IEEE
Inductive cross-talk within IC packaging is becoming a significant bottleneck in high-speed inter-chip communication. The parasitic inductance within IC packaging causes bounce o...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ISLPED
2007
ACM
13 years 8 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy effic...
HICSS
2009
IEEE
14 years 1 months ago
2009
IEEE
This paper addresses the problem of reactive power dispatch in a power system partitioned into several areas controlled by different transmission system operators. Previous resear...