114 search results - page 6 / 23 » Address Register Assignment for Reducing Code Size |
CASES
2004
ACM
14 years 23 days ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
LCTRTS
1999
Springer
13 years 11 months ago
1999
Springer
Code space is a critical issue facing designers of software for embedded systems. Many traditional compiler optimizations are designed to reduce the execution time of compiled cod...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the...
ASPDAC
2004
ACM
14 years 23 days ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
IEEEPACT
1998
IEEE
13 years 11 months ago
1998
IEEE
Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important ...