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» Address generation for memories containing multiple arrays
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CIKM
2006
Springer
13 years 11 months ago
Heuristic containment check of partial tree-pattern queries in the presence of index graphs
The wide adoption of XML has increased the interest of the database community on tree-structured data management techniques. Querying capabilities are provided through tree-patter...
Dimitri Theodoratos, Stefanos Souldatos, Theodore ...
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 7 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
IPPS
2003
IEEE
14 years 22 days ago
Global Communication Optimization for Tensor Contraction Expressions under Memory Constraints
The accurate modeling of the electronic structure of atoms and molecules involves computationally intensive tensor contractions involving large multi-dimensional arrays. The effi...
Daniel Cociorva, Xiaoyang Gao, Sandhya Krishnan, G...
ISCA
2009
IEEE
150views Hardware» more  ISCA 2009»
14 years 2 months ago
Stream chaining: exploiting multiple levels of correlation in data prefetching
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
Pedro Diaz, Marcelo Cintra
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 11 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...