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DATE
2003
IEEE
101views Hardware» more  DATE 2003»
14 years 2 months ago
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
In this paper, we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic rout...
Jingcao Hu, Radu Marculescu
ICMLA
2007
13 years 10 months ago
Improving gene expression programming performance by using differential evolution
Gene Expression Programming (GEP) is an evolutionary algorithm that incorporates both the idea of a simple, linear chromosome of fixed length used in Genetic Algorithms (GAs) and...
Qiongyun Zhang, Chi Zhou, Weimin Xiao, Peter C. Ne...
ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
14 years 1 months ago
Simultaneous buffer and wire sizing for performance and power optimization
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
JNW
2007
75views more  JNW 2007»
13 years 9 months ago
Improving and Analyzing LC-Trie Performance for IP-Address Lookup
— IP-address lookup is a key processing function of Internet routers. The lookup is challenging because it needs to perform a longest prefix match. In this paper, we present our...
Jing Fu, Olof Hagsand, Gunnar Karlsson
DATE
2009
IEEE
242views Hardware» more  DATE 2009»
14 years 3 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...