Sciweavers

3456 search results - page 40 / 692
» Algorithms for Interface Synthesis
Sort
View
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
DAC
2001
ACM
14 years 8 months ago
Using Symbolic Algebra in Algorithmic Level DSP Synthesis
Armita Peymandoust, Giovanni De Micheli
IPPS
1998
IEEE
13 years 12 months ago
Synthesis of a Systolic Array Genetic Algorithm
The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm exp...
Graham M. Megson, I. M. Bland
ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
13 years 12 months ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi
GECCO
2003
Springer
14 years 27 days ago
Problem-Independent Schema Synthesis for Genetic Algorithms
Abstract. As a preprocessing for genetic algorithms, static reordering helps genetic algorithms effectively create and preserve high-quality schemata, and consequently improves th...
Yong-Hyuk Kim, Yung-Keun Kwon, Byung Ro Moon