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DATE
2006
IEEE
118views Hardware» more  DATE 2006»
14 years 1 months ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...
DAC
2005
ACM
14 years 8 months ago
MiniBit: bit-width optimization via affine arithmetic
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the intege...
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayn...
ARITH
2007
IEEE
14 years 1 months ago
How to Ensure a Faithful Polynomial Evaluation with the Compensated Horner Algorithm
The compensated Horner algorithm improves the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic: the computed result is as accurate as if it was computed wi...
Philippe Langlois, Nicolas Louvet
COMPGEOM
2001
ACM
13 years 11 months ago
Computing a 3-dimensional cell in an arrangement of quadrics: exactly and actually!
We present two approaches to the problem of calculating a cell in a 3-dimensional arrangement of quadrics. The first approach solves the problem using rational arithmetic. It work...
Nicola Geismann, Michael Hemmer, Elmar Schöme...
DAC
1996
ACM
13 years 11 months ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant