120 search results - page 4 / 24 » An Accurate Interconnection Length Estimation for Computer L... |
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
VLSISP
2008
13 years 8 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is ...
PERCOM
2010
ACM
14 years 13 days ago
2010
ACM
—AutoGait is a mobile platform that autonomously discovers a user’s walking profile and accurately estimates the distance walked. The discovery is made by utilizing the GPS in...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...