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MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 2 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
TVLSI
2008
153views more  TVLSI 2008»
13 years 7 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
CASES
2010
ACM
13 years 5 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
ISCA
2005
IEEE
104views Hardware» more  ISCA 2005»
14 years 1 months ago
Opportunistic Transient-Fault Detection
CMOS scaling increases susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use full redundancy to achieve perfect coverage ...
Mohamed A. Gomaa, T. N. Vijaykumar