248 search results - page 12 / 50 » An Analog Leaf Cell for Analog Circuit Design |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
DATE
2005
IEEE
14 years 27 days ago
2005
IEEE
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...