161 search results - page 5 / 33 » An Analysis of Delay Based PUF Implementations on FPGA |
TVLSI
2008
13 years 7 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
ISLPED
1996
ACM
13 years 12 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
FPGA
2000
ACM
13 years 11 months ago
2000
ACM
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
SERSCISA
2010
Springer
13 years 9 months ago
2010
Springer
The delay and dispersion of the packet train have been widely used in most network measurement tools. The timestamp of the packet is critical for the measurement accuracy. However...
ISCAS
2002
IEEE
14 years 18 days ago
2002
IEEE
FPGAs are an attractive platform for elliptic curve cryptography hardware. Since field multiplication is the most critical operation in elliptic curve cryptography, we have studi...