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» An Architecture for Exploring Large Design Spaces
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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 2 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
IPPS
2010
IEEE
13 years 5 months ago
Large neighborhood local search optimization on graphics processing units
Local search (LS) algorithms are among the most powerful techniques for solving computationally hard problems in combinatorial optimization. These algorithms could be viewed as &q...
Thé Van Luong, Nouredine Melab, El-Ghazali ...
CODES
1999
IEEE
14 years 1 days ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
ICRA
2006
IEEE
225views Robotics» more  ICRA 2006»
14 years 1 months ago
Constraint Optimization Coordination Architecture for Search and Rescue Robotics
— The dangerous and time sensitive nature of a disaster area makes it an ideal application for robotic exploration. Our long term goal is to enable humans, software agents, and a...
Mary Koes, Illah R. Nourbakhsh, Katia P. Sycara
DAC
2008
ACM
13 years 9 months ago
Technology exploration for graphene nanoribbon FETs
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale proc...
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik...