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DAC
2006
ACM
14 years 9 months ago
Scheduling-based test-case generation for verification of multimedia SoCs
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The v...
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ron...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 9 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
14 years 9 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
CGO
2009
IEEE
14 years 3 months ago
Software Pipelined Execution of Stream Programs on GPUs
—The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. This model allows programmers to sp...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
IEEEPACT
2009
IEEE
14 years 3 months ago
Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of...
Tipp Moseley, Dirk Grunwald, Ramesh Peri