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ISCAS
2006
IEEE
144views Hardware» more  ISCAS 2006»
14 years 5 months ago
A VLSI spike-driven dynamic synapse which learns only when necessary
— We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is hi...
S. Mitra, Stefano Fusi, Giacomo Indiveri
BMCBI
2010
227views more  BMCBI 2010»
13 years 11 months ago
Accurate and efficient gp120 V3 loop structure based models for the determination of HIV-1 co-receptor usage
Background: HIV-1 targets human cells expressing both the CD4 receptor, which binds the viral envelope glycoprotein gp120, as well as either the CCR5 (R5) or CXCR4 (X4) co-recepto...
Majid Masso, Iosif I. Vaisman
DATE
2008
IEEE
76views Hardware» more  DATE 2008»
14 years 5 months ago
Front End Device for Content Networking
The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. T...
Jeremy Buboltz, Taskin Koçak
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 3 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 11 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri