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» An Efficient Hardware Support for Control Data Validation
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ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 7 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ASAP
2007
IEEE
116views Hardware» more  ASAP 2007»
13 years 9 months ago
The Design of a Novel Object-oriented Processor : OOMIPS
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
Weixing Ji, Feng Shi, Baojun Qiao, Muhammad Kamran
ECRTS
2007
IEEE
13 years 11 months ago
Statistical QoS Guarantee and Energy-Efficiency in Web Server Clusters
In this paper we study the soft real-time web cluster architecture needed to support e-commerce and related applications. Our testbed is based on an industry standard, which defin...
Luciano Bertini, Julius C. B. Leite, Daniel Moss&e...
VLSISP
2010
205views more  VLSISP 2010»
13 years 6 months ago
Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA
— This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, s...
Dimitris G. Bariamis, Dimitris Maroulis, Dimitrios...
DATE
2006
IEEE
73views Hardware» more  DATE 2006»
14 years 1 months ago
Minimizing test power in SRAM through reduction of pre-charge activity
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hash...