113 search results - page 13 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
ICNP
2003
IEEE
14 years 21 days ago
2003
IEEE
CAMs are the most popular practical method for implementing packet classification in high performance routers. Their principal drawbacks are high power consumption and inefficient...