113 search results - page 21 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
ISCAS
2003
IEEE
14 years 20 days ago
2003
IEEE
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
TVLSI
2008
13 years 7 months ago
2008
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...