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BMCBI
2005
126views more  BMCBI 2005»
13 years 7 months ago
Integrative analysis of multiple gene expression profiles with quality-adjusted effect size models
Background: With the explosion of microarray studies, an enormous amount of data is being produced. Systematic integration of gene expression data from different sources increases...
Pingzhao Hu, Celia M. T. Greenwood, Joseph Beyene
ICCAD
1997
IEEE
106views Hardware» more  ICCAD 1997»
13 years 12 months ago
BIST TPG for faults in system backplanes
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...
Chen-Huan Chiang, Sandeep K. Gupta
FPL
2006
Springer
103views Hardware» more  FPL 2006»
13 years 11 months ago
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures
Reconfigurable architectures are becoming increasingly popular with space related design engineers as they are inherently flexible to meet multiple requirements and offer signific...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
DAC
2003
ACM
14 years 26 days ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
TCAD
2008
172views more  TCAD 2008»
13 years 7 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...