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» An Embedded IDDQ Testing Architecture and Technique
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TVLSI
2002
98views more  TVLSI 2002»
13 years 6 months ago
Minimizing memory access energy in embedded systems by selective instruction compression
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...
DAC
1999
ACM
13 years 11 months ago
Microprocessor Based Testing for Core-Based System on Chip
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC. The novel feature of the approach is the use an embedde...
Christos A. Papachristou, F. Martin, Mehrdad Noura...
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
14 years 5 days ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
JRTIP
2008
300views more  JRTIP 2008»
13 years 6 months ago
Real-time human action recognition on an embedded, reconfigurable video processing architecture
Abstract In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a realtime, emb...
Hongying Meng, Michael Freeman, Nick Pears, Chris ...
ATS
2002
IEEE
101views Hardware» more  ATS 2002»
13 years 11 months ago
An Access Timing Measurement Unit of Embedded Memory
As the deep sub-micron techniques evolving, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to the access limitations. ...
Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang