28 search results - page 4 / 6 » An Enhanced Multilevel Algorithm for Circuit Placement |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
FPL
1997
Springer
13 years 11 months ago
1997
Springer
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
FPGA
2004
ACM
14 years 27 days ago
2004
ACM
As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalab...
ISPD
2007
ACM
13 years 9 months ago
2007
ACM
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...