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» An Evidential Tool Bus
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DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 5 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
FPL
2007
Springer
125views Hardware» more  FPL 2007»
14 years 5 months ago
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro
Reconfigurable computing entails the utilization of a generalpurpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete recon...
Stefan Raaijmakers, Stephan Wong
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 4 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 3 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
FUZZIEEE
2007
IEEE
14 years 2 months ago
A System for Querying with Qualitative Distances in Networks
A central role of Geographic Information Systems (GIS) is to allow the identification and visualisation of relevant spatial features from typically large volumes of data. This requ...
Carl P. L. Schultz, Hans W. Guesgen, Robert Amor