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JUCS
2008
153views more  JUCS 2008»
13 years 11 months ago
Bus Network Optimization with a Time-Dependent Hybrid Algorithm
: This paper describes a new hybrid technique that combines a Greedy Randomized Adaptive Search Procedure (GRASP) and a genetic algorithm with simulation features in order to solve...
Ana C. Olivera, Mariano Frutos, Jessica Andrea Car...
ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
14 years 3 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello
DAC
1991
ACM
14 years 2 months ago
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...
Jerry P. Hwang
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
14 years 2 months ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
13 years 2 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...