96 search results - page 4 / 20 » An Experimental Chip to Evaluate Test Techniques: Chip and E... |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
ITC
2003
IEEE
14 years 18 days ago
2003
IEEE
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
IJCAI
1989
13 years 8 months ago
1989
This paper presents an evaluation of two orthogonal schemes for improving the efficiency of solving constraint satisfaction problems (CSPs). The first scheme involves a class of p...
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 5 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
EH
2003
IEEE
14 years 19 days ago
2003
IEEE
This paper presents experimental results of fast intrinsic evolutionary design and evolutionary fault recovery of a 4-bit Digital to Analog Converter (DAC) using the JPL stand-alo...