260 search results - page 18 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
ERSA
2010
13 years 5 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
ICMCS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...