1079 search results - page 79 / 216 » An Implementation of an Address Generator Using Hash Memorie... |
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
ITC
2003
IEEE
14 years 2 months ago
2003
IEEE
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract--In this article we present KRASH, a tool for reproducible generation of system-level CPU load. This tool is intended for use in shared memory machines equipped with multi...
IACR
2011
12 years 8 months ago
2011
Abstract. GOST 28147-89 is a well-known block cipher and the official encryption standard of the Russian Federation. Its large key size of 256 bits at a particularly low implementa...