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» An Input Output HMM Architecture
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DAC
2002
ACM
14 years 8 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
SPAA
2006
ACM
14 years 1 months ago
Packet-mode emulation of output-queued switches
Most common network protocols (e.g., the Internet Protocol) work with variable size packets, whereas contemporary switches still operate with fixed size cells, which are easier t...
Hagit Attiya, David Hay, Isaac Keslassy
DAC
2008
ACM
13 years 9 months ago
DeMOR: decentralized model order reduction of linear networks with massive ports
Model order reduction is an efficient technique to reduce the system complexity while producing a good approximation of the input-output behavior. However, the efficiency of reduc...
Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie C...
AES
2008
Springer
133views Cryptology» more  AES 2008»
13 years 7 months ago
Alternative neural networks to estimate the scour below spillways
Artificial neural networks (ANN's) are associated with difficulties like lack of success in a given problem and unpredictable level of accuracy that could be achieved. In eve...
H. Md. Azamathulla, M. C. Deo, P. B. Deolalikar
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
14 years 29 days ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir