54 search results - page 5 / 11 » An Instruction Throughput Model of Superscalar Processors |
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
ISPASS
2006
IEEE
14 years 1 months ago
2006
IEEE
Despite years of study, branch mispredictions remain as a significant performance impediment in pipelined superscalar processors. In general, the branch misprediction penalty can...
ISLPED
2003
ACM
14 years 26 days ago
2003
ACM
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
IEEEPACT
1999
IEEE
13 years 12 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...