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EVOW
2001
Springer
15 years 9 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
16 years 4 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 11 months ago
Optimal sizing of configurable devices to reduce variability in integrated circuits
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) st...
Peter Wilson, Reuben Wilcock
ISSE
2010
15 years 2 months ago
URDAD as a semi-formal approach to analysis and design
The Use Case, Responsibility Driven Analysis and Design (URDAD) methodology is a methodology for technology neutral design generating the Platform Independent Model of the Object M...
Fritz Solms, Dawid Loubser
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
15 years 10 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...