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EVOW
2001
Springer
14 years 4 days ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) st...
ISSE
2010
13 years 6 months ago
2010
The Use Case, Responsibility Driven Analysis and Design (URDAD) methodology is a methodology for technology neutral design generating the Platform Independent Model of the Object M...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...